This invention relates to integrated circuits, and more particularly to combining control-signal pins with a differential clock.
Many systems include several integrated circuits (ICs) or chips that communicate with one another over signal lines that can include address, data, and control signal lines. Often one or more clock signals are applied to some chips to synchronize signaling. For example, a microprocessor or microcontroller may send address and control signals to a memory, which responds with data. A memory clock can be generated by the microprocessor or by a clock chip and used to synchronize the data transfer.
FIG. 1 illustrates clock and control signals between a pair of chips. Transmitter chip 10 generates control signals A, B, C which are sent to receiver chip 12 to control its operation. A clock generated by clock generator 14 is sent from transmitter chip 10 to receiver chip 12. This clock can be used to synchronize operations such as receiving control and address signals or sending data between chips 10, 12.
The clock signal can be re-synchronized by Phase-locked loop (PLL) 16 in receiver chip 12. Other internal clocks that are synched to the input clock from transmitter chip 10 can be generated by PLL 16. These internal clocks can have different frequencies yet still be synchronized to the input clock.
The control signals A, B, C are often relatively slow signals such as reset, chip-select, mode-select, etc., but can include more-rapidly-changing signals such as byte-enables and masks, strobes and latch signals. For example, when transmitter chip 10 is a microcontroller or a memory controller, and receiver chip 12 is a memory such as a synchronous dynamic-random-access memory (DRAM), control signals can include reset, chip-select, and output-enable. Many other control signals may be included such as data or address strobes and mask signals, as well as an address and data bus.
FIG. 2A shows a pair of chips with a differential clock. As clock speeds increase, traditional full-voltage-swing signaling can limit the clock speed. Reduced-voltage-swing signaling is sometimes used, often with differential signaling rather than using a single clock line.
Clock generator 14 in transmitter chip 10 generates a single-ended clock XCLK, which is input to differential driver 22. Differential driver 22 generates a differential clock that uses a pair of clock lines CK+, CK− that are output to receiver chip 12. The pair of clock lines CK+, CK− change in opposite directions to signal clock transitions.
Lines CK+, CK− are received by differential receiver 24 inside receiver chip 12. A single-ended receive clock RCLK is generated by differential receiver 24. PLL 16 receives RCLK as an input clock and generates internal clock ICLK. Control signals A, B, C can be synchronized to XCLK in transmitter chip 10 and to ICLK in receiver chip 12, as well as other signals (not shown) such as address, data, and strobe signals.
FIG. 2B is a timing diagram highlighting differential clocking of the chips of FIG. 2A. Transmitter-chip clock XCLK in transmitter chip 10 can be a free-running clock that drives the differential driver which generates differential clock signals CK+, CK−. When a positive (rising-edge) transition of XCLK occurs, CK+ rises while CK− falls. For a negative (falling-edge) transition of XCLK occurs, CK+ falls while CK− rises. The amount of voltage change depends on the driver's current drive and the line's termination.
The differential receiver in receiver chip 12 receives CK+, CK− and generates RCLK with a full-voltage swing. The internal PLL retimes RCLK to generate ICLK. ICLK (and other clocks such as XCLK) can be at the same frequency as RCLK, or can be at a different frequency such as half or one-quarter the RCLK frequency, or even a multiple such as double the RCLK frequency. Control signals such as control signal A can be generated by logic driven by XCLK and sampled by latches or logic using ICLK. These control signals are often active for many clock periods.
As memory chips and systems become more complex, more control signals are needed to control the additional operating features. Larger memories also tend to have more address and data signals. The number of pins available in an IC package may be limited, and for cost-reduction reasons the number of pins may be further limited even though larger, more expensive packages could be used. Thus reducing the number of pins on an IC is desirable. The use of differential clocks is desirable to increase clock speed and noise immunity.